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1 ltc1415 12-bit, 1.25msps, 55mw sampling a/d converter u a o pp l ic at i ty p i ca l 1.25mhz, 12-bit sampling a/d converter , ltc and lt are registered trademarks of linear technology corporation. effective bits and signal-to-(noise + distortion) vs input frequency s f ea t u re n 1.25msps sample rate n single 5v supply n power dissipation: 55mw n nap and sleep power shutdown modes n 0.35lsb inl and 0.25lsb dnl n 72db s/(n + d) and 80db thd at 100khz n external or internal reference operation n true differential inputs reject common mode noise n input range: 4.096v (1mv/lsb) n 28-pin ssop and so packages d u escriptio the ltc ? 1415 is a 700ns, 1.25msps, 12-bit sampling a/d converter that draws only 55mw from a single 5v supply. this easy-to-use device includes a high dynamic range sample-and-hold, precision reference and a trimmed internal clock. two power shutdown modes provide flex- ibility for low power systems. the ltc1415s full-scale input range is 4.096v. low linearity errors 0.35lsb inl, 0.25lsb dnl make it ideal for imaging systems. outstanding ac performance includes 72db s/(n + d) and 80db thd with an input frequency of 100khz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 18mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has a m p compatible, 12-bit parallel output port. there is no pipeline delay in the conversion results. a separate convert start input and data ready signal (busy) ease connections to fifos, dsps and microprocessors. a separate output logic supply pin allows direct connection to 3v components. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d11(msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd dv dd ov dd busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3 ltc1415 10 m f differential analog input (0v to 4.096v) 2.50v v ref output 10 m f 5v 12-bit parallel bus m p control lines 1415 ta01 output logic supply 3v or 5v input frequency (hz) 1k effective bits signal/(noise + distortion) (db) 12 11 10 9 8 7 6 5 4 3 2 1 0 74 68 62 56 10k 100k ltc1415 ?ta02 1m 2m nyquist frequency f sample = 1.25msps u s a o pp l ic at i n high speed data acquisition n imaging systems n digital signal processing n multiplexed data acquisition systems n telecommunications
2 ltc1415 av dd = dv dd =ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................ 6v analog input voltage (note 3) ...... C 0.3v to v dd + 0.3v digital input voltage (note 4) .................. C 0.3v to 12v digital output voltage .................... C 0.3v to v dd + 0.3v power dissipation ............................................. 500mw operating temperature range LTC1415C............................................... 0 c to 70 c ltc1415i ........................................... C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c a u g w a w u w a r b s o lu t exi t i s wu u package / o rder i for atio order part number parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 7) l 0.35 1 lsb differential linearity error l 0.25 1 lsb offset error (note 8) 1 6 lsb l 8 lsb full-scale error 20 lsb full-scale tempco i out(ref) = 0 15 ppm/ c cc hara terist ics co u verter with internal reference (notes 5, 6) symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v l 4.096 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions 19 pf during conversions 5 pf t acq sample-and-hold acquisition time l 50 150 ns t ap sample-and-hold aperture delay time C1.5 ns t jitter sample-and-hold aperture delay time jitter 2 ps rms cmrr analog input common mode rejection ratio 0v < v cm < v dd , dc to mhz 60 db (note 5) put u i a a u log 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 +a in ? in v ref refcomp agnd d11 (msb) d10 d9 d8 d7 d6 d5 d4 dgnd av dd dv dd ov dd busy cs convst rd shdn nap/slp ognd d0 d1 d2 d3 sw package 28-lead plastic so wide g package 28-lead plastic ssop top view consult factory for military grade parts. LTC1415Cg LTC1415Csw ltc1415ig ltc1415isw t jmax = 110 c, q ja = 95 c/w (g) t jmax = 110 c, q ja = 130 c/w (sw)
3 ltc1415 symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 100khz input signal 72 db 600khz input signal 69 db thd total harmonic distortion 100khz input signal, first 5 harmonics C 80 db 600khz input signal, first 5 harmonics C 72 db sfdr spurious free dynamic range 600khz input signal C 75 db imd intermodulation distortion f in1 = 29.37khz, f in2 = 32.446khz C 84 db full-power bandwidth 18 mhz full-linear bandwidth s/(n + d) 3 68db 1 mhz (note 5) accuracy ic dy u w a parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0 15 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.01 lsb/v v ref output resistance ? i out ? 0.1ma 2 k w refcomp output voltage i out = 0 4.096 v digital i puts a d digital outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 5pf v oh high level output voltage v dd = 4.75v i o = C 10 m a 4.5 v i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v i o = 160 m a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d11 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d11 to d0 cs high (note 9 ) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma power require e ts w u (note 5) symbol parameter conditions min typ max units v dd supply voltage (notes 10, 11) 4.75 5.25 v i dd supply current cs high l 11 20 ma nap mode shdn = 0v, nap/slp = 5v (note 12) l 1.5 2.3 ma sleep mode shdn = 0v, nap/slp = 0v (note 12) 1.0 m a p d power dissipation cs high 55 100 mw nap mode shdn = 0v, nap/slp = 5v 7.5 12 mw sleep mode shdn = 0v, nap/slp = 0v 0.01 mw (note 5) (note 5) i ter al refere ce characteristics u uu
4 ltc1415 (note 5) ti i g characteristics w u the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together unless otherwise noted. note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below ground or above v dd without latchup. note 4: when these pin voltages are taken below ground, they will be clamped by internal diodes. this product can handle input currents greater than 100ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 1.25mhz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended +a in input with C a in grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling edge of convst starts a conversion. if convst returns high at a critical point during the conversion it can create small errors. for best performance ensure that convst returns high either within 425ns after the start of the conversion or after busy rises. note 12: cs = rd = convst = 0v. symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 1.25 mhz conversion and acquisition time l 800 ns t conv conversion time l 700 ns t acq acquisition time l 150 ns t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 10 ns t 3 nap/slp - to shdn setup time (notes 9, 10) 200 ns t 4 shdn - to convst wake-up time nap mode (note 10) 200 ns sleep mode, c refcomp = 10 m f (note 10) 10 ms t 5 convst low time (notes 10, 11) l 50 ns t 6 convst to busy delay c l = 25pf 10 ns l 60 ns t 7 data ready before busy - 20 35 ns l 15 ns t 8 delay between conversions (note 10) l 50 ns t 9 wait time rd after busy - l C5 ns t 10 data access time after rd c l = 25pf 20 35 ns l 45 ns c l = 100pf 25 45 ns l 60 ns t 11 bus relinquish time 10 30 ns 0 c = t a = 70 c l 35 ns C40 c = t a = 85 c l 40 ns t 12 rd low time l t 10 ns t 13 convst high time l 50 ns t 14 aperture delay of sample-and-hold C 1.5 ns
5 ltc1415 typical perfor m a n ce characteristics u w input frequency (hz) signal/(noise + distortion) (db) 80 70 60 50 40 30 20 10 0 1k 100k 1m 2m ltc1415 ?tpc01 10k v in = 0db v in = 20db v in = 60db s/(n + d) vs input frequency and amplitude input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 ltc1415 ?tpc03 thd 2nd 3rd 1k 100k 1m 2m 10k distortion vs input frequency input frequency (hz) signal-to -noise ratio (db) 80 70 60 50 40 30 20 10 0 1k ltc1415 ?tpc02 100k 1m 2m 10k signal-to-noise ratio vs input frequency spurious-free dynamic range vs input frequency intermodulation distortion plot input frequency (hz) 10k spurious-free dynamic range (db) 0 10 20 30 40 50 60 70 80 ?0 100k 1m 2m ltc1415 ?tpc04 frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 200k 300k 600k ltc1415 ?tpc05 100k 400k 500k fb ?fa 2fb ?fa 2fa ?fb 2fa 2fb 3fb fa + 2fb 3fa 2fa + fb fa + fb f sample = 1.25mhz f in1 = 86.97509766khz f in2 = 113.2202148khz integral nonlinearity vs output code output code 0 inl error (lsbs) 1.00 0.50 0.00 0.50 1.00 512 1024 1536 ltc1415 ?tpc07 2048 2560 3072 3584 4096 differential nonlinearity vs output code output code 0 dnl error (lsbs) 1.00 0.50 0.00 0.50 1.00 512 1024 1536 ltc1415 ?tpc06 2048 2560 3072 3584 4096
6 ltc1415 typical perfor m a n ce characteristics u w input common mode rejection vs input frequency power supply feedthrough vs ripple frequency ripple frequency (hz) amplitude of power supply feedthrough (db) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 2m ltc1415 ?tpc08 10k v dd ov dd dgnd input frequency (hz) common mode rejection (db) 80 70 60 50 40 30 20 10 0 1k 100k 1m 2m ltc1415 ?tpc09 10k pi fu ctio s uu u rd (pin 22): read input. this enables the output drivers when cs is low. convst (pin 23): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 24): the chip select input must be low for the adc to recognize convst and rd inputs. busy (pin 25): the busy output shows the converter status. it is low when a conversion is in progress. its rising edge may be used to latch the output data. 0v dd (pin 26): digital output buffer supply. short to pin 28 for 5v output. tie to 3v for driving 3v logic. dv dd (pin 27): 5v positive supply. short to pin 28. av dd (pin 28): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. +a in (pin 1): positive analog input, 0v to 4.096v. Ca in (pin 2): negative analog input, 0v to 4.096v. v ref (pin 3): 2.50v reference output. refcomp (pin 4): bypass to agnd with 10 m f tantalum in parallel with 0.1 m f or 10 m f ceramic. agnd (pin 5): analog ground. d11 to d4 (pins 6 to 13): three-state data outputs. dgnd (pin 14): digital ground. d3 to d0 (pins 15 to 18): three-state data outputs. ognd (pin 19): digital output buffer ground. nap/slp (pin 20): power shutdown mode. high for quick wake-up nap mode. shdn (pin 21): power shutdown input. a low logic level will invoke the shutdown mode selected by the nap/slp pin. tie high if unused.
7 ltc1415 12-bit capacitive dac comp ref amp 2.5v ref refcomp (4.096v) c sample c sample ? ? d11 ov dd ognd d0 busy control logic cs convst rd shdn internal clock nap/slp zeroing switches dv dd av dd +a in ? in v ref agnd dgnd 12 1415 bd + successive approximation register output latches 2k fu ctio al block diagra uu w load circuits for access timing load circuits for bus relinquish time 1k 100pf 100pf dbn (a) v oh to hi-z (b) v ol to hi-z dbn 1k 5v 1415 tc02 1k c l c l dbn (a) hi-z to v oh and v ol to v oh (b) hi-z to v ol and v oh to v ol dbn 1k 5v 1415 tc01 test circuits
8 ltc1415 applicatio n s i n for m atio n wu u u conversion details the ltc1415 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to microproces- sors and dsps (please refer to digital interface section for the data format). conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 12-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). referring to figure 1, the +a in and Ca in inputs are con- nected to the sample-and-hold capacitors (c sample ) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 150ns will provide enough time for the sample- and-hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches the connect c sample capacitors to ground, trans- ferring the differential analog input charge onto the sum- ming junction. this input charge is successively compared with the binary weighted charges supplied by the differen- tial capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differ- ential dac output balances the + a in and C a in input charges. the sar contents (a 12-bit data word) which represents the difference of + a in and C a in are loaded into the 12-bit output latches. dynamic performance the ltc1415 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using a fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1415 fft plot. figure 1. simplified block diagram comp +c sample ? dac ? ? d11 d0 zeroing switches hold hold +a in ? in +c dac ? sample 12 ltc1415 ?f01 + sar output latches +v dac ? dac hold hold sample sample frequency (khz) 0 amplitude (db) 0 20 40 60 80 100 120 100 200 300 400 ltc1415 ?f02 500 600 f sample = 1.25mhz f in = 99.792khz sfdr - 87.5 sinad = 72.1 figure 2. ltc1415 nonaveraged, 4096 point fft signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] or sinad is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2 shows a typical spectral content with a 1.25mhz sampling rate and a 100khz input. the dynamic performance is excellent for input frequencies up to the nyquist limit of 625khz.
9 ltc1415 applicatio n s i n for m atio n wu u u effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 1.25mhz the ltc1415 maintains very good enobs up to the nyquist input frequency of 625khz (refer to figure 3). total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++? 20 234 1 222 2 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 4. the ltc1415 has good distortion performance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by input frequency (hz) effective bits signal/(noise + distortion) (db) 12 11 10 9 8 7 6 5 4 3 2 1 0 74 68 62 56 1k 100k 1m 2m lt1415 ?f03 10k figure 3. effective bits and signal/(noise + distortion) vs input frequency figure 4. distortion vs input frequency frequency (hz) 0 amplitude (db) 0 20 40 60 80 100 120 200k 300k 600k ltc1415 ?f05 100k 400k 500k fb ?fa 2fb ?fa 2fa ?fb 2fa 2fb 3fb fa + 2fb 3fa 2fa + fb fa + fb f sample = 1.25mhz f in1 = 86.97509766khz f in2 = 113.2202148khz figure 5. intermodulation distortion plot input frequency (hz) amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 90 100 1k 100k 1m 2m ltc1415 ?f04 10k thd 2nd 3rd
10 ltc1415 the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa + C nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magni- tude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb log + () = 20 amplitude at (fa + fb) amplitude at fa peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 68db (11 effective bits). the ltc1415 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with fre- quencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1415 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the Ca in input is grounded). the +a in and Ca in inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion the analog inputs draw applicatio n s i n for m atio n wu u u only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1415 inputs can be driven directly. as source impedance increases so will acquisition time (see figure 6). for minimum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 150ns for full throughput rate). source resistance (k w ) 0.01 acquisition time ( m s) 1 1415 f06 0.1 0.01 0.1 110 100 10 figure 6. acquisition time vs source resistance choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 w ) at the closed-loop band- width frequency. for example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz should be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 20mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1415 will depend on the application. generally applications fall into two categories: ac applications where dynamic specifi- cations are most critical and time domain applications where dc accuracy and settling time are most critical.
11 ltc1415 the following list is a summary of the op amps that are suitable for driving the ltc1415, more detailed informa- tion is available in the linear technology databooks and the linearview tm cd-rom. lt ? 1215/lt1216: dual and quad 23mhz, 50v/ m s single supply op amps. single 5v to 15v supplies, 6.6ma specifications, 90ns settling to 0.5lsb. lt1223: 100mhz video current feedback amplifier. 5v to 15v supplies, 6ma supply current. low distortion up to and above 400khz. low noise. good for ac applica- tions. lt1227: 140mhz video current feedback amplifier. 5v to 15v supplies, 10ma supply current. lowest distor- tion at frequencies above 400khz. low noise. best for ac applications. lt1229/lt1230: dual and quad 100mhz current feedback amplifiers. 2v to 15v supplies, 6ma supply current each amplifier. low noise. good ac specs. lt1360: 37mhz voltage feedback amplifier. 5v to 15v supplies. 3.8ma supply current. good ac and dc specs. 70ns settling to 0.5lsb. lt1363: 50mhz, 450v/ m s op amps. 5v to 15v sup- plies. 6.3ma supply current. good ac and dc specs. 60ns settling to 0.5lsb. lt1364/lt1365: dual and quad 50mhz, 450v/ m s op amps. 5v to 15v supplies, 6.3ma supply current per ampli- fier. 60ns settling to 0.5lsb. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1415 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 20mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example figure 7 shows a 1000pf capacitor from +a in to ground and a 100 w source resistor to limit the input bandwidth to 1.6mhz. the 1000pf applicatio n s i n for m atio n wu u u linearview is a trademark of linear technology corporation. capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. ltc1415 +a in ? in v ref refcomp agnd ltc1415 ?f07 1 2 3 4 5 10 m f 1000pf 100 analog input figure 7. rc input filter input range the 4.096v input range of the ltc1415 is optimized for low noise. most single supply op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special transla- tion circuitry. some applications may require other input ranges. the ltc1415 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1415 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500v. it is connected internally to a reference amplifier and is available at v ref (pin 3) see figure 8a. a 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other
12 ltc1415 applicatio n s i n for m atio n wu u u circuitry. the reference amplifier gains the voltage at the v ref pin by 1.638 to create the required internal reference voltage of 4.096v. this provides buffering between the v ref pin and the high speed capacitive dac. the reference amplifier compensation pin (refcomp, pin 4) must be bypassed with a capacitor to ground. the reference ampli- fier is stable with capacitors of 1 m f or greater. for the best noise performance a 10 m f ceramic or tantalum in parallel with a 0.1 m f ceramic is recommended. r2 40k r3 64k reference amp 10 f refcomp agnd v ref r1 2k bandgap reference 3 4 5 2.500v 4.096v ltc1415 ltc1415 ?f08a figure 8a. ltc1415 reference circuit 1 2 3 10 m f analog input 1415 f08b lt1019a-2.5 v out v in 5v +a in ? in v ref ltc1415 agnd refcomp 5 4 figure 8b. using the lt1019-2.5 as an external reference ltc1415 +a in differential analog input range = (v ref )(1.638) ? in v ref refcomp agnd ltc1415 ?f09 1 2 3 4 5 10 m f ltc1450 12-bit rail-to-rail dac 1.25v to 3v figure 9. driving v ref with a dac to adjust full scale bandwidth and settling time of this circuit. a settling time of 5ms should be allowed for after a reference adjustment. differential inputs the ltc1415 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the adc will always convert the difference of +a in C (Ca in ) independent of the common mode voltage. the common mode rejection is constant from dc to 1mhz, see figure 10a. the only requirement is that both inputs can not exceed the av dd or agnd power supply voltages. integral nonlinearity errors (inl) and differential nonlinearity errors (dnl) are independent of the common mode voltage, however, the bipolar zero error (bze) will vary. the change in bze is typically less than 0.1% of the common mode voltage. differential inputs allow greater flexibility for accepting different input ranges. figure 10b shows a circuit that shifts the input range up in voltage by 200mv. this can be useful in applications where the amplifier driving the adc input is not able to swing all the way to ground, because of output loading or settling time issues. some ac applications may have their performance limited by distortion. most circuits exhibit higher distortion when signals approach the supply or ground. distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. the circuit of figure 10c reduces the adc full scale from the v ref pin can be driven with a dac or other means shown in figure 9. this is useful in applications where the peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the filtering of the internal ltc1415 reference amplifier will limit the
13 ltc1415 applicatio n s i n for m atio n wu u u 4.096v to 2.048v and shifts the common mode voltage from half of full scale to 2.274v. ac coupled inputs the analog inputs can be ac coupled for applications where the input has no dc information. the input of the adc does need to be dc biased at midscale. figures 10d and 10e demonstrate ac coupling and the required bias- ing. figure 10d shows the adc with a full scale of 4.096v, a common mode voltage of 2.048v and an input that swings from 0v to 4.096v. this circuit has the lowest noise (sinad = 72db to 100khz) but will have distortion input frequency (hz) signal/(noise + distortion) (db) 80 70 60 50 40 30 20 10 0 1k 100k 1m 2m ltc1415 ?f10a 10k figure 10a. cmrr vs input frequency figure 10b. shifting the input range up from ground by 200mv ltc1415 +a in analog input 1.25v to 3.298v ? in v ref refcomp agnd ltc1415 ?f10c 1 2 3 4 5 10 m f 24 1 m f v out = 1.2v lt1004-1.2 figure 10c. 2.048v input range with a common mode voltage of 2.274v. for low distortion ac applications ltc1415 +a in analog input 4.096v p-p ? in v ref refcomp agnd ltc1415 ?f10d 1 2 3 4 5 10 m f 2k 2k figure 10d. 4.096v p-p input range with ac coupling. for low noise ac applications ltc1415 +a in analog input 2.048v p-p ? in v ref refcomp agnd ltc1415 ?f10e 1 2 3 4 5 10 m f 1 m f 25 1k 9k 1k + lt1004-1.2 figure 10e. 2.048v p-p input range with ac coupling. for low distortion ac applications ltc1415 +a in analog input 0.2v to 4.296v ? in v ref refcomp agnd ltc1415 ?f10b 1 2 3 4 5 10 m f r2 3.9k r1 200
14 ltc1415 applicatio n s i n for m atio n wu u u limitations at high input frequencies (thd = 75db at 600khz). the adc in figure 10e has a full scale of 2.048v and a common mode of 2.27v. the reduced signal swing of this circuit results in improved distortion at higher input frequencies (thd = 82db at 600khz) but with worse sinad at low frequencies (sinad = 70db at 100khz). full-scale and offset adjustment figure 11a shows the ideal input/output characteristics for the ltc1415. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb,... fs C 1.5lsb, fs C 0.5lsb). the output is straight binary with 1lsb = fs/4096 = 4.096v/4096 = 1mv. figure 11b. offset and full-scale adjust circuit analog input ltc1415 ?f11b r4 100 w r1 100 w r3 24k r2 47k r8 50k r7 50k r5 47k r6 24k 0.1 m f 10 m f 5v +a in ? in v ref ltc1415 1 2 3 5 4 agnd refcomp the output code flickers between 1111 1111 1110 and 1111 1111 1111. board layout and grounding wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1415, a printed circuit board with ground plane is required. the ground plane under the adc area should be as free of breaks and holes as possible, such that a low impedance path between all adc grounds and all adc decoupling capacitors is provided. it is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. layout should ensure that digital and analog signal lines are separated as much as possible. particular care should be taken not to run any digital track alongside an analog signal track. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd), pin 14 and pin 19 (adcs dgnd) and all other analog grounds should be connected to this single analog ground point. the refcomp bypass capacitor and the dv dd bypass capacitor should also be connected to this analog ground plane. no other digital grounds should be connected to this analog ground plane. low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figure 11b shows the extra components required for full-scale error adjustment. zero offset is achieved by adjusting the offset applied to the C a in input. for zero offset error apply 0.5mv (i.e., 0.5lsb) at +a in and adjust the offset at the Ca in input (r8) until the output code flickers between 0000 0000 0000 and 0000 0000 0001. for full-scale adjustment, an input voltage of 4.0945v (fs C 1.5lsbs) is applied to the analog input and r7 is adjusted until input voltage (v) output code ltc1415 ?f11a 111...111 111...110 111...101 000...010 000...001 000...000 1lsb fs ?1lsb figure 11a. ltc1415 transfer characteristics
15 ltc1415 applicatio n s i n for m atio n wu u u width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1415 has differential inputs to minimize noise coupling. common mode noise on the + a in and C a in leads will be rejected by the input cmrr. the C a in input can be used as a ground sense for the + a in input; the ltc1415 will hold and convert the difference voltage between + a in and C a in . the leads to + a in (pin 1) and C a in (pin 2) should be kept as short as possible. in applications where this is not possible, the + a in and C a in traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins as shown in the typical application on the fist page of this data sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypass- ing in a small board space. alternatively 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. the layout demon- strates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. ltc1415 ?f12 +a in agnd refcomp av dd dv dd ognd ltc1415 digital system 0.1 m f + analog input circuitry 5 4 2 28 27 ov dd 26 19 dgnd 14 1 0.1 m f 10 m f 10 m f ? in + + analog ground plane figure 12. power supply grounding practice
16 ltc1415 applicatio n s i n for m atio n wu u u d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d11 d11 rdy dgnd dgnd +a in ? in v ref comp busy cs convst rd shdn av dd dv dd ov dd agnd dgnd 6 7 8 9 10 11 12 13 15 16 17 18 19 20 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 2 3 4 25 24 23 22 21 28 27 26 5 14 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ognd nap/slp u2 ltc1415 j6 header 11 12 9 10 7 8 5 6 3 4 1 2 13 14 15 16 b0 to b11 d0 to d11 u3 74hc574 d0 d1 d2 d3 d4 d5 d6 d7 1 11 2 3 4 5 6 7 8 9 b0 b1 b2 b3 b11 b10 b9 b8 b7 b6 b5 b4 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 d0 d1 d2 d3 d11 oe q0 q1 q2 q3 q4 q5 q6 q7 clk u4 74hc574 d0 d1 d2 d3 d4 d5 d6 d7 1 11 2 3 4 5 6 7 8 9 d10 d9 d8 d7 d6 d5 d4 oe q0 q1 q2 q3 q4 q5 q6 q7 clk jp4d jp4c jp4b jp4a d0 r0 to r11 1.2k 12 u5a hc14 u5b hc14 34 13 12 u5f hc14 11 10 u5e hc14 r14 1k u5d hc14 c8 1000pf c3 1000pf c4 1000pf notes: unless otherwise specified 1. all resistor value in ohms, 1/10w, 5% 2. all capacitor values in m f, 25v, 20% and in pf, 50v, 10% c10 10 m f 16v c2 10 m f 16v c6 10 m f 16v c12 0.1 m f c13 15pf c5 1 m f 16v + v cc v cc ov dd 3.3v jp2a jp2b r12 20 w c9 0.1 m f c1 22 m f 10v v cc ov dd ov dd 14 7 v cc r15 51 w r16 51 w jp3 j7 clk j5 ? in j3 +a in j2 7v to 15v j1 gnd j4 optional r19 10k r20 10k r13 51 w r17 1m tab u1 lt1121-5 1 4 2 agnd dgnd 3 3.3v v in v out gnd d15 ss12 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 c11 0.1 m f c7 10 m f 10v + nap/slp shdn rd cs r18 1m jp1 led 98 ltc1415 ?f13a u5c hc14 56 u5g hc14 v cc gnd figure 13a. suggested evaluation circuit schematic
17 ltc1415 applicatio n s i n for m atio n wu u u figure 13c. suggested evaluation circuit board component side layout figure 13b. suggested evaluation circuit board component side silkscreen
18 ltc1415 applicatio n s i n for m atio n wu u u figure 13d. suggested evaluation circuit board solder side layout digital interface the a/d converter is designed to interface with micropro- cessors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. a separate convst is used to initiate a conversion. internal clock the a/d converter has an internal clock that eliminates the need of synchronization between the external clock and the cs and rd signals found in other adcs. the internal clock is factory trimmed to achieve a typical conversion time of 0.70 m s and a maximum conversion time over the full operating temperature range of 0.75 m s. no external adjustments are required. the guaranteed maximum acquisition time is 150ns. in addition, a throughput time of 800ns and a minimum sampling rate of 1.25msps are guaranteed. power shutdown the ltc1415 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power by 87% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 200ns. follow the setup time shown in figure 14a to avoid inadvertently invoking sleep mode. in sleep mode all bias currents are shut down and only leakage current remains, about 1 m a. wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accu- racy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 10ms with the recommended 10 m f capacitor. shutdown is controlled by pin 21 (shdn); the adc is in shutdown when it is low. the shutdown mode is selected with pin 20 (nap/slp); high selects nap. figure 14a. nap/slp to shdn timing t 3 nap/slp shdn 1415 f14a
19 ltc1415 u s a o pp l ic at i wu u i for atio in slow memory and rom modes (figures 19 and 20) cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor applies a logic low to rd (= convst), starting the conversion. busy goes low, forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results ap- pear on the data outputs; busy goes high, releasing the processor and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion. t 4 shdn convst 1415 f14b figure 14b. shdn to convst wake-up timing timing and control conversion start and data read operations are controlled by three digital inputs: convst, cs and rd. a logic 0 applied to the convst pin will start a conversion after the adc has been selected (i.e., cs is low). once initiated, it cannot be restarted until the conversion is complete. converter status is indicated by the busy output. busy is low during a conversion. figures 16 through 20 show several different modes of operation. in modes 1a and 1b (figures 16 and 18) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 18) cs is tied low. the falling edge of the convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared mpu databus. figure 15. cs to convst setup timing t 2 t 1 cs convst rd 1415 ?f15 data (n ?1) db11 to db0 convst busy 1415 ?f16 t 5 t conv t 6 t 8 t 7 data n db11 to db0 data (n + 1) db11 to db0 data figure 16. mode 1a convst starts a conversion. data outputs always enabled
20 ltc1415 u s a o pp l ic at i wu u i for atio figure 17. mode 1b convst starts a conversion. data is read by rd data (n ?1) db11 to db0 convst busy 1415 ?f17 t conv t 6 t 13 t 7 data n db11 to db0 data (n + 1) db11 to db0 data t 5 t 6 t 6 t 8 convst busy 1415 f18 t 5 t conv t 8 t 13 t 6 t 9 t 12 data n db11 to db0 t 11 t 10 rd data figure 18. mode 2 convst starts a conversion. data is read by rd
21 ltc1415 u s a o pp l ic at i wu u i for atio rd = convst busy 1415 ?f19 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 data (n + 1) db11-db0 data n db11 to db0 t 11 t 8 t 10 t 7 figure 19. slow memory mode timing rd = convst busy cs = 0 1415 ?f20 t conv t 6 data (n ?1) db11 to db0 data data n db11 to db0 t 10 t 11 t 8 figure 20. rom mode timing
22 ltc1415 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
23 ltc1415 u package d e sc r i pti o dimensions in inches (millimeters) unless otherwise noted. sw package 28-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s28 (wide) 0996 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ note 1 0.697 ?0.712* (17.70 ?18.08) 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 25 26 11 12 22 21 20 19 18 17 16 15 23 24 14 13 27 28 note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24 ltc1415 ? linear technology corporation 1996 1415f lt/tp 0497 7k ? printed in usa related parts part number description comments ltc1273/75/76 complete 5v sampling 12-bit adcs lower power 75mw and cost effective for f sample 300ksps with 70db sinad at nyquist ltc1274/77 low power 12-bit adcs with nap lowest power (10mw) for f sample 100ksps and sleep mode shutdown ltc1278/79 high speed sampling 12-bit adcs cost effective 12-bit adcs with convert start input with shutdown best for 300ksps < f sample 600ksps ltc1282 complete 3v 12-bit adc with fully specified for 3v-powered applications, f sample 140ksps 12mw power dissipation ltc1409 low power 12-bit, 800ksps sampling adc best dynamic performance, f sample 800ksps, 80mw dissipation ltc1410 12-bit, 1.25msps sampling adc best dynamic performance, thd = 84 and sinad = 71 at nyquist with shutdown ltc1419 14-bit, 800ksps sampling adc 81.5db sinad, 150mw from 5v supplies ltc1605 16-bit, 100ksps sampling adc single supply, 10v input range, low power linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com

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